CMPBRANCH_INSTRS=CMPBRANCH_INSTRS_0, DIVIDE_INSTRS=DIVIDE_INSTRS_0, DEBUG_INSTRS=DEBUG_INSTRS_0, BITFIELD_INSTRS=BITFIELD_INSTRS_0, BITCOUNT_INSTRS=BITCOUNT_INSTRS_0, COPROC_INSTRS=COPROC_INSTRS_0
Instruction Set Attributes Register 0
| BITCOUNT_INSTRS | Indicates the supported Bit Counting instructions 0 (BITCOUNT_INSTRS_0): None supported, ARMv7-M unused 1 (BITCOUNT_INSTRS_1): Adds support for the CLZ instruction |
| BITFIELD_INSTRS | Indicates the supported BitField instructions 0 (BITFIELD_INSTRS_0): None supported, ARMv7-M unused 1 (BITFIELD_INSTRS_1): Adds support for the BFC, BFI, SBFX, and UBFX instructions |
| CMPBRANCH_INSTRS | Indicates the supported combined Compare and Branch instructions 0 (CMPBRANCH_INSTRS_0): None supported, ARMv7-M unused 1 (CMPBRANCH_INSTRS_1): Adds support for the CBNZ and CBZ instructions |
| COPROC_INSTRS | Indicates the supported Coprocessor instructions 0 (COPROC_INSTRS_0): None supported, except for separately attributed architectures, for example the Floating-point extension 1 (COPROC_INSTRS_1): Adds support for generic CDP, LDC, MCR, MRC, and STC instructions 2 (COPROC_INSTRS_2): As for 1, and adds support for generic CDP2, LDC2, MCR2, MRC2, and STC2 instructions 3 (COPROC_INSTRS_3): As for 2, and adds support for generic MCRR and MRRC instructions 4 (COPROC_INSTRS_4): As for 3, and adds support for generic MCRR2 and MRRC2 instructions |
| DEBUG_INSTRS | Indicates the supported Debug instructions 0 (DEBUG_INSTRS_0): None supported, ARMv7-M unused 1 (DEBUG_INSTRS_1): Adds support for the BKPT instruction |
| DIVIDE_INSTRS | Indicates the supported Divide instructions 0 (DIVIDE_INSTRS_0): None supported, ARMv7-M unused 1 (DIVIDE_INSTRS_1): Adds support for the SDIV and UDIV instructions |